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<title>UNPCKHPS—Unpack and Interleave High Packed Single-Precision Floating-Point Values </title></head>
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<h1>UNPCKHPS—Unpack and Interleave High Packed Single-Precision Floating-Point Values</h1>
<table>
<tr>
<td>
<p><strong>Opcode/Instruction</strong></p>
<p>RM</p>
<p>UNPCKHPS xmm1, xmm2/m128</p></td>
<th>Op /En</th>
<td>
<p><strong>64/32 bit Mode Support</strong></p>
<p>V/V</p></td>
<td>
<p><strong>CPUID Feature Flag</strong></p>
<p>SSE</p></td>
<td>
<p><strong>Description</strong></p>
<p>Unpacks and Interleaves single-precision floating-point values from high quadwords of xmm1 and xmm2/m128.</p></td></tr>
<tr>
<td>
<p>VEX.NDS.128.0F.WIG 15 /r</p>
<p>VUNPCKHPS xmm1, xmm2, xmm3/m128</p></td>
<td>RVM</td>
<td>V/V</td>
<td>AVX</td>
<td>Unpacks and Interleaves single-precision floating-point values from high quadwords of xmm2 and xmm3/m128.</td></tr>
<tr>
<td>
<p>VEX.NDS.256.0F.WIG 15 /r</p>
<p>VUNPCKHPS ymm1, ymm2, ymm3/m256</p></td>
<td>RVM</td>
<td>V/V</td>
<td>AVX</td>
<td>Unpacks and Interleaves single-precision floating-point values from high quadwords of ymm2 and ymm3/m256.</td></tr>
<tr>
<td>
<p>EVEX.NDS.128.0F.W0 15 /r</p>
<p>VUNPCKHPS xmm1 {k1}{z}, xmm2, xmm3/m128/m32bcst</p></td>
<td>FV</td>
<td>V/V</td>
<td>AVX512VL AVX512F</td>
<td>Unpacks and Interleaves single-precision floating-point values from high quadwords of xmm2 and xmm3/m128/m32bcst and write result to xmm1 subject to writemask k1.</td></tr>
<tr>
<td>
<p>EVEX.NDS.256.0F.W0 15 /r</p>
<p>VUNPCKHPS ymm1 {k1}{z}, ymm2, ymm3/m256/m32bcst</p></td>
<td>FV</td>
<td>V/V</td>
<td>AVX512VL AVX512F</td>
<td>Unpacks and Interleaves single-precision floating-point values from high quadwords of ymm2 and ymm3/m256/m32bcst and write result to ymm1 subject to writemask k1.</td></tr>
<tr>
<td>
<p>EVEX.NDS.512.0F.W0 15 /r</p>
<p>VUNPCKHPS zmm1 {k1}{z}, zmm2, zmm3/m512/m32bcst</p></td>
<td>FV</td>
<td>V/V</td>
<td>AVX512F</td>
<td>Unpacks and Interleaves single-precision floating-point values from high quadwords of zmm2 and zmm3/m512/m32bcst and write result to zmm1 subject to writemask k1.</td></tr></table>
<h3>Instruction Operand Encoding</h3>
<table>
<tr>
<td>Op/En</td>
<td>Operand 1</td>
<td>Operand 2</td>
<td>Operand 3</td>
<td>Operand 4</td></tr>
<tr>
<td>RM</td>
<td>ModRM:reg (r, w)</td>
<td>ModRM:r/m (r)</td>
<td>NA</td>
<td>NA</td></tr>
<tr>
<td>RVM</td>
<td>ModRM:reg (w)</td>
<td>VEX.vvvv (r)</td>
<td>ModRM:r/m (r)</td>
<td>NA</td></tr>
<tr>
<td>FV</td>
<td>ModRM:reg (w)</td>
<td>EVEX.vvvv (r)</td>
<td>ModRM:r/m (r)</td>
<td>NA</td></tr></table>
<p><strong>Description</strong></p>
<p>Performs an interleaved unpack of the high single-precision floating-point values from the first source operand and the second source operand.</p>
<p>128-bit Legacy SSE version: The second source can be an XMM register or an 128-bit memory location. The desti-nation is not distinct from the first source XMM register and the upper bits (MAX_VL-1:128) of the corresponding ZMM register destination are unmodified. When unpacking from a memory operand, an implementation may fetch only the appropriate 64 bits; however, alignment to 16-byte boundary and normal segment checking will still be enforced.</p>
<p>VEX.128 encoded version: The first source operand is a XMM register. The second source operand can be a XMM register or a 128-bit memory location. The destination operand is a XMM register. The upper bits (MAX_VL-1:128) of the corresponding ZMM register destination are zeroed.</p>
<p>VEX.256 encoded version: The second source operand is an YMM register or an 256-bit memory location. The first source operand and destination operands are YMM registers.</p>
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<h3>Figure 4-27.  VUNPCKHPS Operation</h3>
<p>EVEX.512 encoded version: The first source operand is a ZMM register. The second source operand is a ZMM register, a 512-bit memory location, or a 512-bit vector broadcasted from a 32-bit memory location. The destina-tion operand is a ZMM register, conditionally updated using writemask k1.</p>
<p>EVEX.256 encoded version: The first source operand is a YMM register. The second source operand is a YMM register, a 256-bit memory location, or a 256-bit vector broadcasted from a 32-bit memory location. The destina-tion operand is a YMM register, conditionally updated using writemask k1.</p>
<p>EVEX.128 encoded version: The first source operand is a XMM register. The second source operand is a XMM register, a 128-bit memory location, or a 128-bit vector broadcasted from a 32-bit memory location. The destina-tion operand is a XMM register, conditionally updated using writemask k1.</p>
<p><strong>Operation</strong></p>
<p><strong>VUNPCKHPS (EVEX encoded version when SRC2 is a register)</strong></p>
<p>(KL, VL) = (4, 128), (8, 256), (16, 512)</p>
<p>IF VL &gt;= 128</p>
<p>TMP_DEST[31:0] (cid:197) SRC1[95:64]</p>
<p>TMP_DEST[63:32] (cid:197) SRC2[95:64]</p>
<p>TMP_DEST[95:64] (cid:197) SRC1[127:96]</p>
<p>TMP_DEST[127:96] (cid:197) SRC2[127:96]</p>
<p>FI;</p>
<p>IF VL &gt;= 256</p>
<p>TMP_DEST[159:128] (cid:197) SRC1[223:192]</p>
<p>TMP_DEST[191:160] (cid:197) SRC2[223:192]</p>
<p>TMP_DEST[223:192] (cid:197) SRC1[255:224]</p>
<p>TMP_DEST[255:224] (cid:197) SRC2[255:224]</p>
<p>FI;</p>
<p>IF VL &gt;= 512</p>
<p>TMP_DEST[287:256] (cid:197) SRC1[351:320]</p>
<p>TMP_DEST[319:288] (cid:197) SRC2[351:320]</p>
<p>TMP_DEST[351:320] (cid:197) SRC1[383:352]</p>
<p>TMP_DEST[383:352] (cid:197) SRC2[383:352]</p>
<p>TMP_DEST[415:384] (cid:197) SRC1[479:448]</p>
<p>TMP_DEST[447:416] (cid:197) SRC2[479:448]</p>
<p>TMP_DEST[479:448] (cid:197) SRC1[511:480]</p>
<p>TMP_DEST[511:480] (cid:197) SRC2[511:480]</p>
<p>FI;</p>
<p>FOR j (cid:197) 0 TO KL-1</p>
<p>i (cid:197) j * 32</p>
<p>IF k1[j] OR *no writemask*</p>
<p>THEN DEST[i+31:i] (cid:197) TMP_DEST[i+31:i]</p>
<p>ELSE</p>
<p>IF *merging-masking*</p>
<p>; merging-masking</p>
<p>THEN *DEST[i+31:i] remains unchanged*</p>
<p>ELSE *zeroing-masking*</p>
<p>; zeroing-masking</p>
<p>DEST[i+31:i] (cid:197) 0</p>
<p>FI</p>
<p>FI;</p>
<p>ENDFOR</p>
<p>DEST[MAX_VL-1:VL] (cid:197) 0</p>
<p><strong>VUNPCKHPS (EVEX encoded version when SRC2 is memory)</strong></p>
<p>(KL, VL) = (4, 128), (8, 256), (16, 512)</p>
<p>FOR j (cid:197) 0 TO KL-1</p>
<p>i (cid:197) j * 32</p>
<p>IF (EVEX.b = 1)</p>
<p>THEN TMP_SRC2[i+31:i] (cid:197) SRC2[31:0]</p>
<p>ELSE TMP_SRC2[i+31:i] (cid:197) SRC2[i+31:i]</p>
<p>FI;</p>
<p>ENDFOR;</p>
<p>IF VL &gt;= 128</p>
<p>TMP_DEST[31:0] (cid:197) SRC1[95:64]</p>
<p>TMP_DEST[63:32] (cid:197) TMP_SRC2[95:64]</p>
<p>TMP_DEST[95:64] (cid:197) SRC1[127:96]</p>
<p>TMP_DEST[127:96] (cid:197) TMP_SRC2[127:96]</p>
<p>FI;</p>
<p>IF VL &gt;= 256</p>
<p>TMP_DEST[159:128] (cid:197) SRC1[223:192]</p>
<p>TMP_DEST[191:160] (cid:197) TMP_SRC2[223:192]</p>
<p>TMP_DEST[223:192] (cid:197) SRC1[255:224]</p>
<p>TMP_DEST[255:224] (cid:197) TMP_SRC2[255:224]</p>
<p>FI;</p>
<p>IF VL &gt;= 512</p>
<p>TMP_DEST[287:256] (cid:197) SRC1[351:320]</p>
<p>TMP_DEST[319:288] (cid:197) TMP_SRC2[351:320]</p>
<p>TMP_DEST[351:320] (cid:197) SRC1[383:352]</p>
<p>TMP_DEST[383:352] (cid:197) TMP_SRC2[383:352]</p>
<p>TMP_DEST[415:384] (cid:197) SRC1[479:448]</p>
<p>TMP_DEST[447:416] (cid:197) TMP_SRC2[479:448]</p>
<p>TMP_DEST[479:448] (cid:197) SRC1[511:480]</p>
<p>TMP_DEST[511:480] (cid:197) TMP_SRC2[511:480]</p>
<p>FI;</p>
<p>FOR j (cid:197) 0 TO KL-1</p>
<p>i (cid:197) j * 32</p>
<p>IF k1[j] OR *no writemask*</p>
<p>THEN DEST[i+31:i] (cid:197) TMP_DEST[i+31:i]</p>
<p>ELSE</p>
<p>IF *merging-masking*</p>
<p>; merging-masking</p>
<p>THEN *DEST[i+31:i] remains unchanged*</p>
<p>ELSE *zeroing-masking*</p>
<p>; zeroing-masking</p>
<p>DEST[i+31:i] (cid:197) 0</p>
<p>FI</p>
<p>FI;</p>
<p>ENDFOR</p>
<p>DEST[MAX_VL-1:VL] (cid:197) 0</p>
<p><strong>VUNPCKHPS (VEX.256 encoded version)</strong></p>
<p>DEST[31:0] (cid:197)SRC1[95:64]</p>
<p>DEST[63:32] (cid:197)SRC2[95:64]</p>
<p>DEST[95:64] (cid:197)SRC1[127:96]</p>
<p>DEST[127:96] (cid:197)SRC2[127:96]</p>
<p>DEST[159:128] (cid:197)SRC1[223:192]</p>
<p>DEST[191:160] (cid:197)SRC2[223:192]</p>
<p>DEST[223:192] (cid:197)SRC1[255:224]</p>
<p>DEST[255:224] (cid:197)SRC2[255:224]</p>
<p>DEST[MAX_VL-1:256] (cid:197) 0</p>
<p><strong>VUNPCKHPS (VEX.128 encoded version)</strong></p>
<p>DEST[31:0] (cid:197)SRC1[95:64]</p>
<p>DEST[63:32] (cid:197)SRC2[95:64]</p>
<p>DEST[95:64] (cid:197)SRC1[127:96]</p>
<p>DEST[127:96] (cid:197)SRC2[127:96]</p>
<p>DEST[MAX_VL-1:128] (cid:197)0</p>
<p><strong>UNPCKHPS (128-bit Legacy SSE version)</strong></p>
<p>DEST[31:0] (cid:197)SRC1[95:64]</p>
<p>DEST[63:32] (cid:197)SRC2[95:64]</p>
<p>DEST[95:64] (cid:197)SRC1[127:96]</p>
<p>DEST[127:96] (cid:197)SRC2[127:96]</p>
<p>DEST[MAX_VL-1:128] (Unmodified)</p>
<p><strong>Intel C/C++ Compiler Intrinsic Equivalent</strong></p>
<p>VUNPCKHPS __m512 _mm512_unpackhi_ps( __m512 a, __m512 b);</p>
<p>VUNPCKHPS __m512 _mm512_mask_unpackhi_ps(__m512 s, __mmask16 k, __m512 a, __m512 b);</p>
<p>VUNPCKHPS __m512 _mm512_maskz_unpackhi_ps(__mmask16 k, __m512 a, __m512 b);</p>
<p>VUNPCKHPS __m256 _mm256_unpackhi_ps (__m256 a, __m256 b);</p>
<p>VUNPCKHPS __m256 _mm256_mask_unpackhi_ps(__m256 s, __mmask8 k, __m256 a, __m256 b);</p>
<p>VUNPCKHPS __m256 _mm256_maskz_unpackhi_ps(__mmask8 k, __m256 a, __m256 b);</p>
<p>UNPCKHPS __m128 _mm_unpackhi_ps (__m128 a, __m128 b);</p>
<p>VUNPCKHPS __m128 _mm_mask_unpackhi_ps(__m128 s, __mmask8 k, __m128 a, __m128 b);</p>
<p>VUNPCKHPS __m128 _mm_maskz_unpackhi_ps(__mmask8 k, __m128 a, __m128 b);</p>
<p><strong>SIMD Floating-Point Exceptions</strong></p>
<p>None</p>
<p><strong>Other Exceptions</strong></p>
<p>Non-EVEX-encoded instructions, see Exceptions Type 4.</p>
<p>EVEX-encoded instructions, see Exceptions Type E4NF.</p></body></html>